PA119CE ? PA119CEa pa119u 1 PA119CE, PA119CEa features ? very fast slew rate 900 v/s ? power mos technology 4a peak rating ? low internal losses 0.75v at 2a ? protected output stage thermal shutoff ? wide supply range 15v to 40v applications ? video distribution and amplification ? high speed deflection circuits ? power transducers up to 5 mhz ? modulation of rf power stages ? power led or laser diode excitation description the pa119 is a high voltage, high current operational ampli - fer optimized to drive a variety of loads from dc through the video frequency range. excellent input accuracy is achieved with a dual monolithic fet input transistor which is cascoded by two high voltage transistors to provide outstanding common mode characteristics. all internal current and voltage levels are referenced to a zener diode biased on by a current source. as a result, the pa119 exhibits superior dc and ac stability over a wide supply and temperature range. high speed and freedom from second breakdown is assured by a complementary power mos output stage. for optimum linearity, especially at low levels, the power mos transistors are biased in a class a/b mode. thermal shutoff provides full protection against overheating and limits the heatsink requirements to dissipate the internal power losses under normal operating conditions. a built-in current limit of 0.5a can be increased with the addition of two external resistors. transient inductive load kickback protection is provided by two internal clamping diodes. external phase compensation allows the user maximum fexibility in obtaining the optimum slew rate and gain bandwidth product at all gain settings. a heatsink of proper rating is recommended. this hybrid circuit utilizes thick flm (cermet) resistors, ceramic capacitors, and silicon semiconductor chips to maximize reli - ability, minimize size, and give top performance. ultrasonically bonded aluminum wires provide reliable interconnections at all operating temperatures. the 8-pin to-3 package is hermeti - cally sealed and electrically isolated. the use of compress - ible thermal washers and/or improper mounting torque will void the product warranty. please see general operating considerations. top view 1 2 3 4 5 6 7 8 Cv +in Cin out c c r clC phase compensation c c 330pf 22pf 2.2pf none gain 1 10 100 1000 +v r cl+ typical application this fast power driver utilizes the 900v/s slew rate of the pa119 and provides a unique interface with a current output dac. by using the dacs internal 1k feedback resistor, temperature drift errors are minimized, since the temperature drift coefficients of the internal current source and the internal feedback resistor of the dac are closely matched. gain of v out to i in is C6.5/ma. the dacs internal 1k resistor together with the external 500 and 110 form a tee network in the feedback path around the pa119. this effective resistance equals 6.5k . therefore the entire circuit can be modeled as 6.5k feedback resistor from output to inverting input and a 5ma current source into the inverting input of the pa119. now we see the familiar current to voltage conversion for a dac where v out = Ci in x r feedback . equivalent schematic external connections +40v C40v 32.5v r cl+ pa119 pa119 as fast power driver r clC 5.6pf up to 4a 110 500 5ma 1k dac typical application 8-pin to-3 package style ce 3 6 8 5 4 1 q3 q5 q4 d1 d2 q16 q13 q12 q1 q7 q19 q17b q11 q10 2 7 q15 q20 q24 q25 q21 q22 q9 q8 q2 q17a q23 video power operational amplifier PA119CE ? PA119CEa p r o d u c t i n n o v a t i o n f r o m copyright ? cirrus logic, inc. 2009 (all rights reserved) http://www.cirrus.com may 2009 apex ? pa119urevb p r o d u c t i n n o v a t i o n f r o m
PA119CE ? PA119CEa 2 pa119u specifications absolute maximum ratings supply voltage, +v s to Cv s 80v output current, within soa 5a power dissipation, internal 75w input voltage, differential 40v input voltage, common mode v s temperature, pin solder 10 sec 300c temperature, junction 1 175c temperature, storage C65 to 150c operating temperature range, case C55 to 125c pa119 pa119a parameter test conditions 2 min typ max min typ max units input offset voltage, initial t c = 25c .5 3 .35 .75 mv offset voltage, vs. temperature t c = 25c to +85c 10 30 5 15 v/c offset voltage, vs. supply t c = 25c 10 * v/v offset voltage, vs. power t c = 25c to +85c 20 * v/w bias current, initial t c = 25c 10 200 5 50 pa bias current, vs. supply t c = 25c .01 * pa/v offset current, initial t c = 25c 5 100 3 25 pa input impedance, dc t c = 25c 10 11 * m input capacitance t c = 25c 6 * pf common mode voltage range 3 t c = 25c to +85c v s C15 v s C12 * * v common mode rejection, dc t c = 25c to +85c, v cm = 20v 70 104 * * db gain open loop gain at 10hz t c = 25c, r l = 1k? 111 * db open loop gain at 10hz t c = 25c, r l = 15? 74 88 * * db gain bandwidth product at 1mhz t c = 25c, c c = 2.2pf 100 * mhz power bandwidth, a v = 100 t c = 25c, c c = 2.2pf 3.5 * mhz power bandwidth, a v = 1 t c = 25c, c c = 330pf 250 * khz output voltage swing 3 t c = 25c, i o = 4a v s C5 v s C1.5 * * v voltage swing 3 t c = 25c to +85c, i o = 2a v s C3 v s C.75 * * v voltage swing 3 t c = 25c to +85c, i o = 78ma v s C1 v s C.5 * * v settling time to .1% t c = 25c, 2v step .3 * s settling time to .01% t c = 25c, 2v step 1.2 * s slew rate, a v = 100 t c = 25c, c c = 2.2pf 600 900 750 * v/s slew rate, a v = 10 t c = 25c, c c = 22pf 650 * v/s power supply voltage t c = 25c to +85c 15 35 40 * * * v current, quiescent t c = 25c 100 120 * * ma thermal resistance, ac, junction to case 4 t c = 25c to +85c, f > 60hz 1.46 1.64 * * c/w resistance, dc, junction to case t c = 25c to +85c, f < 60hz 1.84 2.0 * * c/w resistance, junction to air t c = 25c to +85c 30 * c/w temperature range, case meets full range specifcations C25 +85 * * c notes: * the specifcation of pa119a is identical to the specifcation for pa119 in applicable column to the left. 1. long term operation at the maximum junction temperature will result in reduced product life. derate internal power dissipation to achieve high mttf. 2. the power supply voltage for all specifcations is the typ rating unless noted as a test condition. 3. +v s and Cv s denote the positive and negative supply rail respectively. total v s is measured from +v s to Cv s . 4. rating applies if the output current alternates between both output transistors at a rate faster than 60hz. the internal substrate contains beryllia (beo). do not break the seal. if accidentally broken, do not crush, machine, or subject to temperatures in excess of 850c to avoid generating toxic fumes. caution p r o d u c t i n n o v a t i o n f r o m
PA119CE ? PA119CEa pa119u 3 C50 100 1.0 3.0 3.5 current limit 2.0 .5 current limit, i lim (a) C25 25 50 75 2.5 1.5 case temperature, t c (c) 0 0 125 r cl = 0.27 w w r cl = 1.2 r cl = 10 common mode voltage common mode voltage, v cm (v pCp ) 45 100 1k 10k 100k 1m 50 55 60 65 70 40 10m frequency, f (hz) frequency, f (hz) output voltage, v (v ) o power response pp 21 30 41 58 15 1m 20m 100k 200k 2m 4m 8m 600k 80 11 8 c c = 2.2pf c c = 22pf c c = 330pf | +v s | + | Cv s | = 80v r l = 15 w 0 output voltage swing output current, i o (a) voltage drop from supply (v) 1 2 3 4 5 +v Cv 100 100m frequency, f (hz) C20 0 60 small signal response open loop gain, a ol (db) 20 40 80 100 1k 100k 10k 1m 10m 2.2pf 22pf 330pf compensation capacitor, c c (pf) slew rate vs. comp. slew rate, (v/s) 10 100 400 2 4 20 40 200 40 100 200 600 400 1000 800 6 60 80 r l = 15 w 200 time, t (ns) C30 C20 30 pulse response output voltage, v o (v) C10 20 C50 0 50 100 150 10 0 250 300 r l = 15 w v in = 2v a v = 10 t r = 10ns 30 60 80 total supply voltage, v s (v) 1.4 quiescent current 1.2 40 50 70 .6 .8 normalized quiescent current, i q (x) 1.0 1.6 1k 10m frequency, f (hz) common mode rejection commom mode rejection, cmr (db) 40 80 120 10k 100k 1m 20 60 100 100m 1k frequency, f (hz) power supply rejection power supply rejection, psr (db) 10k 100k 1m 100m 0 20 40 60 80 100 10m 10 100 10k 1m frequency, f (hz) input noise voltage, v n (nv/ hz) input noise 1k 10 15 20 30 7 5 3 100k 0 25 50 75 100 125 case temperature, t c (c) 10 40 60 80 power derating internal power dissipation, p(w) 50 150 70 30 20 0 1.5 1.0 0.5 p r o d u c t i n n o v a t i o n f r o m
PA119CE ? PA119CEa 4 pa119u 1. the current handling capability of the mosfet geometry and the wire bonds. 2. the junction temperature of the output mosfets. the soa curves combine the effect of these limits and allow for internal thermal delays. for a given application, the direc - tion and magnitude of the output current should be calculated or measured and checked against the soa curves. this is simple for resistive loads but more complex for reactive and emf generating loads. the following guidelines may save extensive analytical efforts: 1. capacitive and inductive loads up to the following maximums are safe: v s capacitive load inductive load 40v .1f 11mh 30v 500f 24mh 20v 2500f 75mh 15v 100mh 2. safe short circuit combinations of voltage and current are limited to a power level of 100w. 3. the output stage is protected against transient fyback. however, for protection against sustained, high energy fyback, external fast-recovery diodes should be used. supply current the pa119 features a class a/b driver stage to charge and discharge gate capacitance of q7 and q19. as these currents approach 0.5a, the savings of quiescent current over that of a class a driver stage is considerable. however, supply current drawn by the pa119, even with no load, varies with slew rate of the output signal as shown below. output leads keep the output leads as short as possible. in the video frequency range, even a few inches of wire have signifcant inductances, raising the interconnection impedance and limit - ing the output current slew rate. furthermore, the skin effect increases the resistance of heavy wires at high frequencies. multistrand litz wire is recommended to carry large video currents with low losses. general please read application note 1 "general operating con - siderations" which covers stability, supplies, heat sinking, mounting, current limit, soa interpretation, and specifcation interpretation. visit www.cirrus.com for design tools that help automate tasks such as calculations for stability, internal power dissipation, current limit; heat sink selection; apex precision powers complete application notes library; technical seminar workbook; and evaluation kits. current limit q2 (and q25) limit output current by turning on and remov - ing gate drive when voltage on pin 2 (pin 7) exceeds .65v dif - ferential from the positive (negative) supply rail. with internal resistors equal to 1.2, current limits are approximately 0.5a with no external current limit resistors. with the addition of external resistors current limit will be: to determine values of external current limit resistors: phase compensation at low gain settings, an external compensation capacitor is required to insure stability. in addition to the resistive feedback network, roll off or integrating capacitors must also be consid - ered when determining gain settings. the capacitance values listed in the external connection diagram, along with good high frequency layout practice, will insure stability. interpolate values for intermediate gain settings. safe operating area (soa) the mosfet output stage of this power operational ampli - fer has two distinct limitations: supply current 400 300 200 100 0 30k 100k 300k 1m 3m 10m frequency, f (hz) supply current, i s (ma) v out = 60v p-p sine r l = 500 i lim = +.54a .65v r cl r cl = .65v i cl C .54a s o a 1 1 0 i n t e r n a l v o l t a g e d r o p s u p p l y t o o u t p u t , v s -v o (v) o u t p u t c u r r e n t f r o m + v s or -v s 2 4 3 t c = 2 5 c 1 0 2 0 3 0 4 0 5 0 8 0 5 100 t = 100ms t = 300ms steady state p r o d u c t i n n o v a t i o n f r o m
PA119CE ? PA119CEa pa119u 5 thermal shutdown the thermal protection circuit shuts off the amplifer when the substrate temperature exceeds approximately 150c. this allows the heatsink selection to be based on normal operating conditions while protecting the amplifer against excessive junction temperature during temporary fault conditions. thermal protection is a fairly slow-acting circuit and therefore does not protect the amplifer against transient soa violations (areas outside of the steady state boundary). it is designed to protect against short-term fault conditions that result in high power dissipation within the amplifer. if the conditions that cause thermal shutdown are not removed, the amplifer will oscillate in and out of shutdown. this will result in high peak power stresses, destroy signal integrity, and reduce the reli - ability of the device. stability due to its large bandwidth, the pa119 is more likely to oscillate than lower bandwidth power operational amplifers. to prevent oscillations a reasonable phrase margin must be maintained by: 1. selection of the proper phase compensation capacitor. use the values given in the table under external connections and interpolate if necessary. the phase margin can be increased by using a larger capacitor at the expense of slew rate. total physical length (pins of the pa119, capacitor leads plus printed circuit traces) should be limited to a maximum of 3.5 inches. 2. keep the external sumpoint stray capacitance to ground at a minimum and the sumpoint load resistance (input and feedback resistors in parallel) below 500. larger sumpoint load resistances can be used with increased phase com - pensation and/or by bypassing the feedback resistor. 3. connect the case to any ac ground potential. cont acting cirrus logic support for all apex precision power product questions and inquiries, call toll free 800-546-2739 in north america. for inquiries via email, please contact apex.support@cirrus.com. international customers can also request support by contacting their local cirrus logic sales representative. to fnd the one nearest to you, go to www.cirrus.com important notice cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnifcation, and limitation of liability. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the information contained herein and gives con - sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe prop - erty or environmental damage (critical applications). cirrus products are not designed, authorized or warranted to be suitable for use in products surgically implanted into the body, automotive safety or security devices, life support prod - ucts or other critical applications. inclusion of cirrus products in such applications is understood to be fully at the cus - tomers risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantability and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or customers customer uses or permits the use of cirrus products in critical applications, customer agrees, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any and all liability, including attorneys fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs, apex precision power, apex and the apex precision power logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. p r o d u c t i n n o v a t i o n f r o m
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